Optimization of substrate doping for back-gate control in SOI T-RAM memory technology

Author

Ershov, M. ; Nemati, F. ; Gupta, R. ; Gopalakrishnan, V. ; Gooty, R. ; Tarabbia, M. ; Yang, K.J. ; Banna, S. ; Hayes, D. ; Cho, H.-J. ; Robins, S.

Author_Institution

T-RAM Semicond., San Jose, CA, USA

fYear

2005

fDate

3-6 Oct. 2005

Firstpage

215

Lastpage

216

Abstract

This paper presents various considerations for substrate doping optimization in SOI T-RAM technology. Back gate (substrate voltage) control is used in an SOI T-RAM technology for optimizing cell characteristics. However, it is reported for the first time that typical low-doped substrates used in SOI logic technologies can create unusually slow transient effects in T-RAM cell. It is also demonstrated that the optimization of substrate doping resolves this slow transient problem and improves back gate control of SOI T-RAM memory arrays.

Keywords

random-access storage; semiconductor doping; silicon-on-insulator; thyristors; SOI T-RAM memory arrays; SOI T-RAM memory technology; SOI logic technologies; back-gate control; low-doped substrates; substrate doping optimization; substrate voltage control; transient effects; CMOS technology; Logic arrays; MOSFETs; Random access memory; Semiconductor device doping; Substrates; Temperature; Threshold voltage; Thyristors; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2005. Proceedings. 2005 IEEE International

ISSN

1078-621X

Print_ISBN

0-7803-9212-4

Type

conf

DOI

10.1109/SOI.2005.1563593

Filename

1563593