Parasitic source/drain resistance reduction in n-channel SOI MuGFETs with 15nm wide fins

We report on a set of process improvements leading to parasitic S/D resistance reduction in n-channel MuGFETs with 60 nm tall and 15 nm wide fins. We experimentally determine the contributions to the parasitic S/D resistance arising from the specific regions of the S/D geometry. A 50% reduction in the S/D resistance (from 1235 to 600 Ω-μm) is achieved by introducing various scaled processes, including EOT reduction, elevated S/D, undoped fins and removal of halos, reduction in S/D spacer width, and smaller gate lengths. The combination of these process enhancements leads to a 2× increase in I_DSAT, measured at constant I_OFF (=1nA/μm) and V_DD=1.3V.