DocumentCode
2840827
Title
On-the-fly sending: a low latency high bandwidth message transfer mechanism
Author
Tanabe, Noboru ; Yamamoto, Junji ; Nishi, Hiroaki ; Kudoh, Tomohiro ; Hamada, Yoshihiro ; Nakajo, Hironori ; Amano, Hideharu
Author_Institution
RWCP Tsukuba Res. Center, Japan
fYear
2000
fDate
2000
Firstpage
186
Lastpage
193
Abstract
Low latency high bandwidth network interface architectures are described. This paper proposes two types of architectures, atomic on-the-fly (OTF) sending with a header TLB, and block on-the-fly sending with protection stampable window memory. These techniques work very effectively with MEMOnet which is a class of network interface card (NIC) plugged into a memory slot. We are developing a network interface controller LSI called Martini. The Martini chip is used in two prototype network interface cards, DIMMnet-I based on MEMOnet, and RHiNET-2/NI based on PCI. On a DIMMnet-I, the software overhead needed to generate a message is only 1 CPU cycle and the estimated hardware delay is less than 100 ns using atomic OTF sending. The estimated achievable sending bandwidth of DIMMnet-I using block OTF sending is 984 MB/s which was observed in our experiments. This bandwidth is 7.4 times higher than the maximum bandwidth of PCI. This excellent performance is available for cheap personal computers with DIMM slots. This paper also describes the effects of block OTF sending for a PCI-based NIC
Keywords
message passing; network interfaces; parallel processing; DIMMnet-I; MEMOnet; Martini; PCI; RHiNET-2/NI; atomic on-the-fly sending; block on-the-fly sending; hardware delay; header TLB; low latency high bandwidth message transfer mechanism; low latency high bandwidth network interface architectures; memory slot; network interface card; network interface controller LSI; personal computers; protection stampable window memory; sending bandwidth; software overhead; Bandwidth; Central Processing Unit; Delay estimation; Hardware; Large scale integration; Microcomputers; Network interfaces; Protection; Prototypes; Software prototyping;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Architectures, Algorithms and Networks, 2000. I-SPAN 2000. Proceedings. International Symposium on
Conference_Location
Dallas, TX
ISSN
1087-4089
Print_ISBN
0-7695-0936-3
Type
conf
DOI
10.1109/ISPAN.2000.900284
Filename
900284
Link To Document