Design of a correlated Lognormal distributed sequence generator based on Virtex-IV series FPGA

Proposed is a hardware correlated Lognormal distributed sequence generator based on the Virtex-IV XC4VFX100-10 FPGA. The random number is generated by the improved Tausworthe architecture and the non-correlated Gaussian random sequence is generated by Box-Muller algorithm. The correlated Lognormal distributed sequence is generated by zero memory non-linearity transformation with the proposed digital architecture. The complex cepstrum is used in the proposed frequency filter to generate the correlated coefficient. The logarithmic and exponential functions are calculated with CORDIC IPCore. The implementation on FPGA occupies 4210 slices, 4 block RAM and 2 DSP48s. The numeral experiment show the feasibility and accuracy of the proposed method. This proposed Lognormal distributed sequence generator can be used as a key component in a hardware radar echo and clutter simulator.