Title :
CMOS ADC with reconfigurable properties for a cellular handset
Author :
Stojcevski, A. ; Singh, J. ; Zayegh, A.
Author_Institution :
Sch. of Electr. Eng., Victoria Univ., Melbourne, Vic., Australia
Abstract :
A low power reconfigurable ADC architecture is described for a mobile terminal receiver. The architecture can automatically scale the resolution by monitoring in-band and out-of-band powers. The architecture performance was evaluated in a simulation UTRA-TDD environment. A power consumption analysis of the implemented architecture is also presented. The UTRA-TDD downlink mode was examined statistically and results show that the reconfigurable architecture can save an average of 74 percent power dissipation for TDD mode when compared to a fixed ADC word length of 16 bits. This will prolong talk and standby time in a mobile terminal.
Keywords :
CMOS integrated circuits; analogue-digital conversion; mobile handsets; power consumption; signal resolution; 16 bit; ADC architecture; CMOS; analog-to-digital converter; cellular handset; complementary metal-oxide-semiconductor; in-band power monitoring; mobile terminal receiver; out-band power monitoring; power consumption analysis; power dissipation; signal resolution; 3G mobile communication; Base stations; Circuit topology; Control systems; Downlink; Energy consumption; Interference; Pipelines; Reconfigurable architectures; Telephone sets;
Conference_Titel :
Electronic Design, Test and Applications, Proceedings. DELTA 2004. Second IEEE International Workshop on
Conference_Location :
Perth, WA, Australia
Print_ISBN :
0-7695-2081-2
DOI :
10.1109/DELTA.2004.10025
