Research on a Low Power Test Generator about Integrated Circuits

With CMOS device into the stage of very deep-submicron, testing power has been an important problem in the VLSI design. In this paper, sources of power consumption for CMOS devices are analyzed and the low power consumption test vector generator of the COMS device is introduced. In order to reduce the switching activity rate of internal nodes in circuit-under-test (CUT), and raise the correlation between testing vector, approaches test vector generator based on the Random Single Input Change (RSIC) test theory and based on a configurable 2D-LFSR are proposed, which can reduce the switching activity rate of nodes in circuit-under-test to realize low power consumption during testing, especially suitable for BIST of COMS device.