Co-simulation of capacitive coupling pads assignment for capacitive coupling interconnection applications

Three dimensions packaging provides a very promising technology for the effective integration of complex systems: devices that are optimally implemented with various different technologies can be separately manufactured and then stacked and connected by means of efficient vertical interconnections over a very short range; this provides most of the benefits of inter-chips for high-bandwidth with a reasonable cost and short development time in the advance of CMOS processes and assembly. This study presents the co-simulation of capacitive coupling pads assignment for the capacitive coupling interconnection. The modelling of a close capacitive coupling interconnection pad is represented by a lumped circuit. The coupling pads of parasitic capacitance are one of the parasitic parameters. The FEM (finite element method) tools simulation results show that the effect of cross-coupling between adjacent channels is dependent on substrate characteristic and pads arrangement. A comparison between simulated and measured circuit performance was shown for a RLC-elements, and qualitative accuracy was obtained. HSPICE tools are applied for the circuit simulations using the equivalent model of coupling pads. Based on the findings of this work, co-simulation methods can reduce simulation time dramatically, the coupling pads assignment can be translated to HSPICE model.