• DocumentCode
    2842357
  • Title

    FPGA-based 112Gb/s coherent DP-QPSK receiver and multi-stage PMD-PDL emulator for fast evaluation of digital signal processing algorithms

  • Author

    Tanimura, Takahito ; Aoki, Yasuhiko ; Nakashima, Hisao ; Hoshida, Takeshi ; Li, Jianqiang ; Tao, Zhenning ; Rasmussen, Jens C.

  • Author_Institution
    Fujitsu Labs. Ltd., Kawasaki, Japan
  • fYear
    2010
  • fDate
    19-23 Sept. 2010
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    We developed an FPGA based 112Gb/s coherent DP-QPSK receiver and a multi-stage PMD-PDL emulator that resembles real fibre conditions. Long-term, low penalty signal reception under severe PMD (31.2ps mean) and PDL (1.3dB mean) is experimentally demonstrated.
  • Keywords
    field programmable gate arrays; polarisation; quadrature phase shift keying; signal processing; FPGA based coherent DP-QPSK receiver; FPGA-based coherent DP-QPSK receiver; digital signal processing; long-term low penalty signal reception; multistage PMD-PDL emulator; real fibre conditions; Couplings; Digital signal processing; Frequency control; Frequency measurement; Q measurement; Receivers; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Optical Communication (ECOC), 2010 36th European Conference and Exhibition on
  • Conference_Location
    Torino
  • Print_ISBN
    978-1-4244-8536-9
  • Electronic_ISBN
    978-1-4244-8534-5
  • Type

    conf

  • DOI
    10.1109/ECOC.2010.5621106
  • Filename
    5621106
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2842357