Development of micro-bump-bonded processes for 3DIC stacking with high throughput

Author

Juang, Jing-Ye ; Lu, Su-Tsai ; Chung, Su-Ching ; Cheng, Su-Mei ; Lu, Yu-Lan ; Peng, Jong-Shiou ; Chen, Tai-Hong

Author_Institution

Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

2011

fDate

19-21 Oct. 2011

Firstpage

366

Lastpage

369

Abstract

Various approaches of high throughput bonding processes were investigated in the micro-bump-bonded processes for 3DIC stacking. The two-step bonding methods, TCB + reflow, TCB + post-bonding and conventional flip-chip process were evaluated in this study. Moreover, the two-step process with different TCB process times (1s, 3s and 5 s) were implemented into the first step. The partial melted joints, which were attained by TCB process, were expected to be fully bonded by the second step (reflow or post-bonding). Then, the temperature cycling test (TCT) was performed to verify reliability performance of the micro-bump-bonded interconnects. Based on the experimental and reliability results, the optimized conditions for the two-step bonding methods and a cost effective solution for the applications of 3DIC stacking can be established.

Keywords

flip-chip devices; integrated circuit bonding; integrated circuit reliability; integrated circuit testing; reflow soldering; three-dimensional integrated circuits; 3DIC stacking; TCB + post-bonding; TCB + reflow; flip-chip devices; micro-bump-bonded interconnects; partial melted joints; reliability performance; temperature cycling test; two-step bonding methods; Bonding; Flip chip; Joints; Reliability; Stacking; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011 6th International

Conference_Location

Taipei

ISSN

2150-5934

Print_ISBN

978-1-4577-1387-3

Electronic_ISBN

2150-5934

Type

conf

DOI

10.1109/IMPACT.2011.6117238

Filename

6117238