High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package

Author

Ryu, Chunghyun ; Chung, Daehyun ; Lee, Junho ; Lee, Kwangyong ; Oh, Taesung ; Kim, Joungho

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea

fYear

2005

fDate

24-26 Oct. 2005

Firstpage

151

Lastpage

154

Abstract

In this paper, we firstly propose the high frequency equivalent circuit model of the chip-to-chip vertical via based on its physical configuration. The model parameters are extracted from the measurement of S-parameters using a vector network analyzer up to 20GHz frequency range. The proposed circuit model is verified experimentally in frequency and time domains. Furthermore, the high frequency characteristics of the chip-to-chip vertical via are investigated.

Keywords

S-parameters; equivalent circuits; integrated circuit interconnections; integrated circuit measurement; integrated circuit modelling; integrated circuit packaging; 3D chip stacking package; S-parameters; chip-to-chip vertical via interconnection; high frequency electrical circuit model; model parameters; vector network analyzer; Capacitance; Coplanar waveguides; Equivalent circuits; Frequency; Integrated circuit interconnections; Packaging; Scattering parameters; Semiconductor device measurement; Silicon; Stacking;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2005. IEEE 14th Topical Meeting on

Print_ISBN

0-7803-9220-5

Type

conf

DOI

10.1109/EPEP.2005.1563724

Filename

1563724