A novel graph partitioning technique for enhancing the computational efficiency of the loop-tree generalized PEEC modeling of 3D interconnects

A novel graph partitioning technique is proposed for the computationally-efficient and numerically robust implementation of a loop-tree, generalized, partial-element-equivalent-circuit (G-PEEC) modeling of the electromagnetic response of interconnect structures. The proposed technique allows for the identification of loops with controllable profiles and the minimum number of associated branches. The resulting G-PEEC model is successfully applied to the electromagnetic modeling of interconnect structures from almost DC to multiple-tens-of-GHz frequencies.