DocumentCode
2843463
Title
Reducing the impact of power supply noise on microprocessor performance
Author
Rahal-Arabi, Tawfik ; Wong, Keng L. ; Ma, Matthew ; Barkatullah, Javed ; Taylor, Greg
Author_Institution
Mobile Platform Archit. Dev., Beaverton, OR, USA
fYear
2005
fDate
24-26 Oct. 2005
Firstpage
307
Lastpage
310
Abstract
In this paper, we demonstrate that it is possible to design circuits insensitive to power supply noise at frequencies in the range of 200 MHz to 500 MHz. We show that by using proper filter design at the beginning of the clock distribution network we increase the clock to data tracking and mitigate the impact of power supply noise on maximum operating frequency. We prove the theory with measurements using a 130 nm processor as an experimental validation vehicle.
Keywords
clocks; integrated circuit noise; microprocessor chips; power supply circuits; 130 nm; 200 to 500 MHz; clock distribution network; data tracking; filter design; microprocessor performance; power supply noise; Circuit noise; Clocks; Delay lines; Frequency; Impedance; Low-frequency noise; Microprocessors; Noise reduction; Phase modulation; Power supplies;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 2005. IEEE 14th Topical Meeting on
Print_ISBN
0-7803-9220-5
Type
conf
DOI
10.1109/EPEP.2005.1563766
Filename
1563766
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