• DocumentCode
    2843499
  • Title

    Failure of lead-free solder joint under thermal cycling

  • Author

    Wang, Yung-Wen ; Wu, Mei-Ling

  • Author_Institution
    Dept. of Mech. & Electro-Mech. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
  • fYear
    2011
  • fDate
    19-21 Oct. 2011
  • Firstpage
    265
  • Lastpage
    268
  • Abstract
    Microelectronic devices are often subjected to environmental and power cycling thermal loads. Thermal cycling and the shear forces lead to many failures in microelectronic devices. The most common failure is an open in one or more of the input/output (I/O). The open is the result of a cracked or damaged interconnects, whether it is a lead-free solder joint. Thermal cycling can occur for a device being turned on and off, a system containing the device being turned on and off, an environmental load, and so on. The most important issue that must be addressed in order to the critical issue is the magnitude of the shear force on the lead-free solder joint under thermal loading, in other words, how many cycles can a microelectronic device survive before a failure occurs. The shear forces are often caused by the global coefficient of thermal expansion (CTE) mismatch between the component and the printed circuit board (PCB). This can be a cyclic load when the microelectronic device is repeatedly subjected to a range of temperatures. Shear forces in the lead-free solder joints are an important aspect of the microelectronic package failure problem because the shear force is directly related to the microelectronic device life. A failure model can be used to predict the fatigue life of a microelectronic device in terms of cycles to failure. The Vandevelde analytic model [1] for determining shear forces in the lead-free solder joints of electronic devices, which is based on elastic strength of materials principles, is critiqued in this paper. This analytic model is then used to gain insightful information regarding interconnect shear force behavior. The results from this new model were compared to finite element model results to assure the analytic model was accurately capturing the behavior of the forces in the lead-free solder joints. The results from the investigations must be qualified by stating that the assumptions of constant pitch, homogeneous component, and linear elas- ic materials were utilized. The completion of this new model leads to a more comprehensive solution to the problem of accurately and efficiently characterizing shear forces in the lead-free solder joint of microelectronic packages and ultimately predicting the life of the packages. Conclusions are made concerning the influence of the number of the lead-free solder joints, device geometry, and material properties on the resulting shear forces. Rapid assessment methodologies for efficiently designing a successful microelectronic package are presented in this paper, which can save both time and money in the design process.
  • Keywords
    fatigue; finite element analysis; integrated circuit interconnections; integrated circuit packaging; printed circuits; solders; thermal expansion; Vandevelde analytic model; cracked interconnects; damaged interconnects; elastic strength; fatigue life; finite element model; input/output; lead-free solder joint; microelectronic device failure; microelectronic package failure problem; printed circuit board; shear forces; thermal cycling; thermal expansion coefficient; thermal loading; Analytical models; Flip chip; Lead; Mathematical model; Soldering; Stress;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011 6th International
  • Conference_Location
    Taipei
  • ISSN
    2150-5934
  • Print_ISBN
    978-1-4577-1387-3
  • Electronic_ISBN
    2150-5934
  • Type

    conf

  • DOI
    10.1109/IMPACT.2011.6117281
  • Filename
    6117281