On-chip bus interleaving revisited

Repeater interleaving is used to reduce the impact of capacitive coupling noise on the worst-case delay in local on-chip RC buses. In this paper, we revisit this interconnect design practice to evaluate it from the viewpoint of signal integrity of global on-chip interconnect used in on-chip high-speed signaling as between a cache and a CPU. Using accurate R(f)L(f)C electrical models of the global bus, we show that the peak crosstalk noise exhibits both monotonic and convex dependence on the interleaving ratio. Furthermore, we show that the worst-case switching pattern used in quantifying the common-mode noise (CMN) on the bus depends on the repeater interleaving ratio. This dependence makes the search of the optimal ratio that minimizes bus CMN quite challenging. The conclusions of this paper are valid for both unidirectional and bidirectional buses.