Logic and functional verification in a commercial semiconductor environment

Functional verification is one of the key bottlenecks in the rapid design of integrated circuits. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources and total personnel. The three primary tools used in logic and functional verification of commercial integrated circuits are simulation (at various levels), emulation at the chip level, and formal verification. While it is not possible to comprehensively survey the field in a short space, current practice in isolated aspects of all three types of verification are discussed. The state of the art in the application of emulation technology to commercial design is discussed. Emulation is proving to be one of the few verification technologies that can address the complexity inherent in full chip designs such as microprocessors and ensures functional first silicon even before design tape-out. We introduce a novel synergism between simulation and formal verification based upon constraints and explain how constraints can be used to replace environment modeling used in formal verification and how they support assume/guarantee reasoning in a mixed simulation/formal verification methodology. Finally, we discuss the successful use of a co-verification tool to develop microprocessor peripherals and develop software drivers for them in a timely way