• DocumentCode
    2843692
  • Title

    ACHIEVING COMPLETE DELAY FAULT TESTABILITY BY EXTRA INPUTS

  • Author

    Pomeranz, Irith ; Reddy, Sudhakar M.

  • fYear
    1991
  • fDate
    26-30 Oct 1991
  • Firstpage
    273
  • Keywords
    Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Delay; Design for testability; Hardware; Logic testing; Minimization; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1991, Proceedings., International
  • ISSN
    1089-3539
  • Print_ISBN
    0-8186-9156-5
  • Type

    conf

  • DOI
    10.1109/TEST.1991.519519
  • Filename
    519519
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2843692