Modelling the saturation region of power bipolar mode JFET for SPICE simulation

Author

Busatto, Giovanni

Author_Institution

IRECE-CNR, Naples, Italy

fYear

1991

fDate

Sept. 28 1991-Oct. 4 1991

Firstpage

1456

Abstract

A circuit model of a power bipolar JFET (junction field-effect transistor) which is able to describe accurately the saturation region of the device both in static and in switching operations is presented. The model permits a good estimate of the device conduction losses and of the device storage time. The equivalent circuit was totally developed on a physical basis, and the extraction of the model parameters can be directly computed from geometrical and physical parameters of the device. The model accurately describes experimental device characteristics and is used to get an insight into the physics of the switching operation of the bipolar JFET in the case of an inductive load.<>

Keywords

bipolar transistors; digital simulation; electronic engineering computing; equivalent circuits; insulated gate field effect transistors; power transistors; semiconductor device models; software packages; switching circuits; JFET; SPICE; bipolar power transistors; characteristics; conduction losses; equivalent circuit; inductive load; saturation region; semiconductor device models; storage time; switching; Analytical models; Circuit simulation; Epitaxial layers; Equivalent circuits; JFET circuits; Physics computing; SPICE; Solid modeling; Substrates; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Industry Applications Society Annual Meeting, 1991., Conference Record of the 1991 IEEE

Conference_Location

Dearborn, MI, USA

Print_ISBN

0-7803-0453-5

Type

conf

DOI

10.1109/IAS.1991.178052

Filename

178052