Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment

Author

Goncharov, Michael V. ; Smirnov, Alexander B. ; Klotchkov, Ilya V. ; Starodoubtsev, Nikolai A.

Author_Institution

Inst. of Anal. Instrum., Acad. of Sci., St. Petersburg, Russia

fYear

1998

fDate

23-26 Mar 1998

Firstpage

120

Lastpage

129

Abstract

This paper includes an overview of the signal transition graph (STG) model extensions that makes it possible to specify switching and signal propagation delays in an STG. The correspondence of the STG timing models to asynchronous circuit implementation is considered. A method to simulate the behavior specified by consistent and bounded timed STG in a VHDL environment is proposed. For illustration the paper presents the possible use of the VHDL-based STG representation in asynchronous circuit design

Keywords

asynchronous circuits; delays; digital simulation; hardware description languages; logic CAD; signal flow graphs; timing; STG model; STG timing models; VHDL; asynchronous circuit design; signal propagation delays; signal transition graph; switching; timed STG behavior simulation; timing extensions; Asynchronous circuits; Circuit simulation; Clocks; Concurrent computing; Delay; Design methodology; Logic design; Logic testing; Signal design; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Application of Concurrency to System Design, 1998. Proceedings., 1998 International Conference on

Conference_Location

Fukushima

Print_ISBN

0-8186-8350-3

Type

conf

DOI

10.1109/CSD.1998.657545

Filename

657545