• DocumentCode
    2844282
  • Title

    A New Look-Up Table Approach for High-Speed Finite Field Multiplication

  • Author

    Meher, Bimal K. ; Meher, Pramod K.

  • Author_Institution
    Dept. of Inf. Technol., Silicon Inst. of Technol., Bhubaneswar, India
  • fYear
    2011
  • fDate
    19-21 Dec. 2011
  • Firstpage
    51
  • Lastpage
    55
  • Abstract
    This paper presents a new high-speed multiplier over GF(2m) based on look-up table (LUT) approach. A straight-forward LUT-based multiplication requires a table of size (m x 2m) bits for the Galois field of order m which is quite large for the fields of large orders recommended by the National Institute of Standards and Technology (NIST). Therefore, in this paper, we propose a digit-serial LUT-based technique, where certain number of operand bits are grouped into digits, and multiplication is performed in serial/parallel manner. We restrict the digit-size to 4 to store only 16 words in the LUT. We have also proposed a digit-parallel design to achieve higher speed than its digit-serial counterpart, which is very much useful for high-speed applications. We have chosen m=233 to satisfy the security requirements in elliptic curve cryptography, but our method can be used for other prime extensions, as well. We have estimated the area-time complexity of our designs in terms of LUT access-time and XOR-delay. The proposed LUT-based implementation will be useful for high-speed applications in elliptic curve cryptography and error control coding.
  • Keywords
    error correction codes; logic gates; public key cryptography; table lookup; Galois field; LUT access-time; LUT approach; NIST; National Institute of Standards and Technology; XOR-delay; area-time complexity; digit-parallel design; digit-serial LUT-based technique; elliptic curve cryptography; error control coding; high-speed finite field multiplication; high-speed multiplier; look-up table approach; straight-forward LUT-based multiplication; Delay; Elliptic curve cryptography; Galois fields; Logic gates; Polynomials; Registers; Table lookup; LUT; digit-parallel; digit-serial; finite field; multiplier;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic System Design (ISED), 2011 International Symposium on
  • Conference_Location
    Kochi, Kerala
  • Print_ISBN
    978-1-4577-1880-9
  • Type

    conf

  • DOI
    10.1109/ISED.2011.35
  • Filename
    6117325