Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications

Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique computational technique for calculations based on 16 Sutras (Formulae). Novel divider architecture for high speed VLSI application using such ancient methodology is presented in this paper. Propagation delay and dynamic power consumption of a divider circuitry were minimized significantly by removing unnecessary recursion through Vedic division methodology. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90nm CMOS technology. The propagation delay of the resulting 16-bit binary dividend by an 8-bit divisor circuitry was only ~10.5ns and consumed ~24ÂμW power for a layout area of ~10.25 mm2. By combining Boolean logic with ancient Vedic mathematics, substantial amount of iteration were eliminated that resulted in ~45% reduction in delay and ~30% reduction in power compared with the mostly used (Digit Recurrence, Convergence & Series Expansion) architectures.