Adiabatic 5T SRAM

In this paper an effort is made to design an energy efficient 5T SRAM in 65nm technology. The energy recovery driver saves energy in the single bit line in addition to enhancing the write ability of the 5T SRAM. The energy recovery is possible by pumping the bit line energy back into the bit line voltage source instead of allowing to ground after write operation. This energy efficient SRAM also provides good performance parameters and hence suitable for high density embedded systems.