Event-driven verification of switch-level correctness concerns

Author

Negulescu, Radu

Author_Institution

Dept. of Comput. Sci., Waterloo Univ., Ont., Canada

fYear

1998

fDate

23-26 Mar 1998

Firstpage

213

Lastpage

223

Abstract

We propose a technique for the verification of MOS circuits, focusing on signal transitions (events) rather than signal levels. Diverse conditions, behaviors, and even delay assumptions are modeled as processes that can be coupled and compared to circuit specifications in a unified formalism. Verification is performed modularly and hierarchically by a BDD-based tool. We illustrate this technique on a self-timed RAM

Keywords

MOS digital integrated circuits; delays; diagrams; formal verification; integrated circuit modelling; logic testing; random-access storage; BDD-based tool; MOS circuit verification; binary decision diagrams; circuit specifications; coupled processes; delay assumptions; event-driven verification; modular hierarchical verification; self-timed RAM; signal transitions; switch-level correctness; Boolean functions; Circuit analysis; Computer science; Data structures; Delay; MOSFETs; Power supplies; Switches; Switching circuits; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Application of Concurrency to System Design, 1998. Proceedings., 1998 International Conference on

Conference_Location

Fukushima

Print_ISBN

0-8186-8350-3

Type

conf

DOI

10.1109/CSD.1998.657553

Filename

657553

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2845405