High Resolution Programmable Digital Delay Generator Design and Realization

Author

Zhaolin, Sun ; Nan, Li ; Yinan, Wang ; Qinghong, Yin ; Xin, Xu ; Jing, Guo ; Haijun, Liu ; Hui, Xu

Author_Institution

ESSS Center, Nat. Univ. of Defense Technol., Changsha, China

Volume

1

fYear

2010

fDate

13-14 Oct. 2010

Firstpage

813

Lastpage

816

Abstract

This article introduced a design principles and implementation method of a high resolution programmable digital delay generator. It described the system´s composition in hardware and software view. This system is composed of deserializer MAX3885, high-speed clock generator AD9517-1, DDR2 SDRAM, serializer and USB2.0 Controller. Paper described FPGA software design methods includes DDR2 SDRAM controller and commands receive module. Modularized design methods are used in FPGA software development, convenient for user´s customization. The DDG system finally achieved 400ps delay time resolution.

Keywords

DRAM chips; field programmable gate arrays; pulse generators; DDG system; DDR2 SDRAM controller; FPGA software design methods; FPGA software development; USB2.0 controller; commands receive module; deserializer MAX3885; high resolution programmable digital delay generator design; high-speed clock generator AD9517-1; Clocks; Delay; Field programmable gate arrays; Generators; SDRAM; Signal resolution; Synchronization; Deseializer; Digital Delay Generator; FPGA; Serializer;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent System Design and Engineering Application (ISDEA), 2010 International Conference on

Conference_Location

Changsha

Print_ISBN

978-1-4244-8333-4

Type

conf

DOI

10.1109/ISDEA.2010.137

Filename

5743304