High Resolution Programmable Digital Delay Generator Design and Realization

This article introduced a design principles and implementation method of a high resolution programmable digital delay generator. It described the system´s composition in hardware and software view. This system is composed of deserializer MAX3885, high-speed clock generator AD9517-1, DDR2 SDRAM, serializer and USB2.0 Controller. Paper described FPGA software design methods includes DDR2 SDRAM controller and commands receive module. Modularized design methods are used in FPGA software development, convenient for user´s customization. The DDG system finally achieved 400ps delay time resolution.