DocumentCode
2846352
Title
Reducing branch misprediction penalty via selective branch recovery
Author
Gandhi, Amit ; Akkary, Haitham ; Srinivasan, Srikanth T.
Author_Institution
Microarchitecture Res. Lab., Intel Corp., USA
fYear
2004
fDate
14-18 Feb. 2004
Firstpage
254
Lastpage
264
Abstract
Branch misprediction penalty consists of two components: the time wasted on misspeculative execution until the mispredicted branch is resolved and the time to restart the pipeline with useful instructions once the branch is resolved. Current processor trends, large instruction windows and deep pipelines, amplify both components of the branch misprediction penalty. We propose a novel method, called selective branch recovery (SBR), to reduce both components of branch misprediction penalty. SBR exploits a frequently occurring type of control independence - exact convergence - where the mispredicted path converges exactly at the beginning of the correct path. In such cases, SBR selectively reuses the results computed during misspeculative execution and obviates the need to fetch or rename convergent instructions again. Thus, SBR addresses both components of branch misprediction penalty. To increase the likelihood of branch mispredictions that can be handled with SBR, we also present an effective means for inducing exact convergence on misspeculative paths. With SBR, we significantly improve performance (between 3%-22%, average 8%) on a wide range of benchmarks over our baseline processor that does not exploit SBR.
Keywords
instruction sets; parallel architectures; pipeline processing; SBR; baseline processor; branch misprediction penalty; convergent instruction; exact convergence; instruction window; misspeculative execution; selective branch recovery; Computer aided instruction; Convergence; Flow graphs; Microarchitecture; Pipelines;
fLanguage
English
Publisher
ieee
Conference_Titel
Software, IEE Proceedings-
ISSN
1530-0897
Print_ISBN
0-7695-2053-7
Type
conf
DOI
10.1109/HPCA.2004.10004
Filename
1410082
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