A low voltage CMOS square law analog multiplier

Author

Tarun, T.B. ; Ismail, Mohammed

Author_Institution

Istanbul Tech. Univ., Turkey

fYear

1999

fDate

1999

Firstpage

5

Lastpage

8

Abstract

A multiplier composed of a low voltage square-law CMOS cell is introduced in this paper. The analysis of the square-law cell is given. The multiplier operates in the saturation region with a fully balanced input signal. Initial simulations were done for 0.8 μm n-well process using BSIM3 model parameters. The circuit has a trade-off between low voltage operation and low power dissipation. The circuit has a cutoff frequency of 99.4 MHz and P_dis=1.5 mW for a bias current of 120 μA. The THD is less then -51 dB and -49 dB for fixed input voltages V3 and V1, respectively, for a 1 MHz, 0.5 V peak-to-peak sinusoidal input

Keywords

CMOS analogue integrated circuits; VLSI; analogue multipliers; 0.5 V; 1 MHz; 1.5 mW; 120 muA; 99.4 MHz; BSIM3 model parameters; CMOS square law analog multiplier; bias current; fixed input voltages; low power dissipation; low voltage operation; peak-to-peak sinusoidal input; saturation region; simulation; square-law cell; trade-off; Circuit simulation; Digital signal processing; Equations; Instruments; Low voltage; MOSFETs; Power dissipation; Semiconductor device modeling; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on

Conference_Location

Tucson, AZ

Print_ISBN

0-7803-5510-5

Type

conf

DOI

10.1109/SSMSD.1999.768581

Filename

768581