Hierarchical modeling of sigma delta modulators for noise coupling analysis

In this paper a hierarchical modeling strategy of a sigma delta modulator for mixed signal coupling analysis is presented. In this hierarchical model only the key components which are important to noise or disturbance analysis are implemented on the transistor level, the other parts are realized in a behavioral model which is written in Analog HDL. The simulation speed can be improved by an order of magnitude. With this method, fast and reasonably accurate estimation for coupled noise in mixed-signal IC design can be achieved. A 5th order sigma delta modulator is used as a demonstration to show the intrinsic noise analysis and the substrate coupling noise analysis