Low power analog fuzzy logic processor

The design and analysis of the consequent and defuzzifier units of a fuzzy logic processor is presented. The circuits have been simulated using BSIM3 parameters for a 0.8 μm CMOS process and utilize the sub-threshold mode of operation of transistors for extremely low power consumption. Design emphasis has been placed on the consequent and defuzzification units because the complexity of computations as well as the concomitant delays indicated that optimizations in these units would improve the overall performance of the processor. Simulation results have shown that power consumption in these two units average about 250 μW and the maximum operating frequency is in the hundreds of kHz