A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters

Author

Gerosa, A. ; Neviani, A. ; Cortelazzo, G.M.

Author_Institution

Dipt. di Elettronica e Inf., Padova Univ., Italy

fYear

1999

fDate

1999

Firstpage

195

Lastpage

198

Abstract

This work presents an architecture for analog implementation of two-dimensional FIR filters. Inner filter delays are realized efficiently by means of an analog RAM, which is accumulating partial convolution products. Furthermore the structure fully exploits the filter impulse response symmetry, reducing silicon area and increasing filter phase linearity. An FIR filter for picture-in-picture applications has been designed in a 0.8 μm CMOS technology, using the proposed architecture. According to simulation results, the system accuracy is within the 8 bit required by video applications

Keywords

CMOS analogue integrated circuits; FIR filters; analogue storage; convolution; delays; random-access storage; switched capacitor filters; transient response; video signal processing; 0.8 micron; 2D SC FIR filters; CMOS technology; delay efficient realization; filter impulse response symmetry; filter phase linearity; inner filter delays; partial accumulation analog-RAM-based architecture; partial convolution products; picture-in-picture applications; video applications; CMOS technology; Capacitors; Circuits; Finite impulse response filter; Hardware; Informatics; Linearity; Propagation delay; Signal generators; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on

Conference_Location

Tucson, AZ

Print_ISBN

0-7803-5510-5

Type

conf

DOI

10.1109/SSMSD.1999.768617

Filename

768617