Title :
Test Power IR Drop Closure Flow for NetComposer-I Platform Design
Author :
Kifli, Augusli ; Chen, W.J. ; Chen, Y.W. ; Wu, K.C.
Author_Institution :
Faraday Technol. Corp., Hsinchu
Abstract :
Power noise has become one of the main culprits in failing chips in SoC designs. As power consumption during scan test can be several times higher than during normal operation, it must be dealt with properly during implementation and testing stages. In this paper, we share some of the test power related experiences we gained through the development of NetComposer platform design. We demonstrate how good power analysis and DFT can help avoid potential power noise issue during test.
Keywords :
discrete Fourier transforms; logic design; logic testing; system-on-chip; DFT; IR drop closure flow; NetComposer-I platform design; SoC design; discrete Fourier transforms; power consumption; power noise; scan test; Cities and towns; Design for testability; Energy consumption; Fluctuations; Image storage; Inductance; Noise generators; Packaging; Switches; Testing;
Conference_Titel :
VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0583-1
Electronic_ISBN :
1-4244-0583-1
DOI :
10.1109/VDAT.2007.373201
