DocumentCode
2847745
Title
Minimizing Energy Consumption with Variable Forward Body Bias for Ultra-Low Energy LSIs
Author
Jayapal, SenthilKumar ; Manoli, Yiannos
Author_Institution
Univ. of Freiburg, Freiburg
fYear
2007
fDate
25-27 April 2007
Firstpage
1
Lastpage
4
Abstract
Ultra-low energy LSI becomes primary concern in today´s battery driven ubiquitous computing portable applications. To reduce energy per transition and to enhance performance in the ultra-low voltage region, we review the variable forward body bias scheme to make either faster pull-up or pull-down transition in the sub-threshold, near-threshold and above-threshold regimes. We begin our study for minimizing energy per transition by applying variable forward body bias asymmetrically and propose novel approaches to energy efficient design with performance advantages. To analyze and discuss, the fan-out of 3 (FO3) inverter based 51-stage delay chain is simulated in an industrial 130 nm triple well process technology.
Keywords
electric potential; integrated circuit design; large scale integration; low-power electronics; ubiquitous computing; 51-stage delay chain; above-threshold regime; battery driven ubiquitous computing portable applications; energy consumption minimisation; energy efficient design; fan-out of 3 inverter; industrial triple well process technology; near-threshold regime; pull-down transition; pull-up transition; size 130 nm; sub-threshold regime; ultra-low energy LSI; ultra-low voltage region; variable forward body bias scheme; Circuits; Clocks; Delay estimation; Energy consumption; Energy efficiency; Equations; Frequency estimation; Inverters; Large scale integration; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on
Conference_Location
Hsinchu
Print_ISBN
1-4244-0583-1
Electronic_ISBN
1-4244-0583-1
Type
conf
DOI
10.1109/VDAT.2007.373206
Filename
4239398
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