DocumentCode
2847883
Title
Topological synthesis procedure for circuit integration
Author
Engl, W. ; Mlynski, D.
Author_Institution
Technische Hochschule Aachen, Aachen, Germany
Volume
XII
fYear
1969
fDate
19-21 Feb. 1969
Firstpage
138
Lastpage
139
Abstract
A computer-aided topological layout of components and wiring in integrated circuits will presented based on a new kind of graph which accounts for all technological restrictions, as well as possibilities.
Keywords
Bonding; Circuit synthesis; Integrated circuit layout; Integrated circuit synthesis; Iterative algorithms; Leg; Packaging; Resistors; Silicon compounds; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1969 IEEE Internationa
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1969.1154721
Filename
1154721
Link To Document