DocumentCode
2848009
Title
Challenges and Solutions in Modern VLSI Placement
Author
Jiang, Zhe-Wei ; Chen, Hsin-Chen ; Chen, Tung-Chieh ; Chang, Yao-Wen
Author_Institution
Nat. Taiwan Univ., Taipei
fYear
2007
fDate
25-27 April 2007
Firstpage
1
Lastpage
5
Abstract
The VLSI placement problem is to place objects into a fixed die such that there are no overlaps among objects and some cost metric (e.g., wirelength, routability) is optimized. It is a major step in physical design that has been studied for decades. However, modern VLSI design challenges have reshaped the placement problem. A modern placer needs to handle large-scale designs with millions of objects, heterogeneous objects with very different sizes, and various complex placement constraints such as preplaced blocks and chip density. In this paper, we first introduce the major techniques employed in our placer for tackling the large-scale mixed-size designs and the aforementioned constraints, and then provide some future research directions for the modern placement problem.
Keywords
VLSI; integrated circuit design; integrated circuit layout; VLSI placement problem; large-scale designs; large-scale mixed-size designs; physical design; Analytical models; Circuits; Cost function; Design methodology; Frequency; Large scale integration; Large-scale systems; Modems; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on
Conference_Location
Hsinchu
Print_ISBN
1-4244-0583-1
Electronic_ISBN
1-4244-0583-1
Type
conf
DOI
10.1109/VDAT.2007.373223
Filename
4239415
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