Power Gating Technique for Embedded Pseudo SRAM

In this paper, we deploy power gating technique on a low-power Pseudo SRAM circuit with 3T1D gain cell. A 256-word x 32-BL-pair 3T1D gain cell array is implemented in standard logic technology with TSMC 0.13 um model for multi-bank Pseudo SRAM. Each Pseudo SRAM has its independent access control unit, enabling parallel refresh and read-write accesses to different bank. By employing power gating technique in sense amplifier of 3T1D gain cell array, 15% standby leakage current during sleep mode could be reduced. Also, 12% sensing speed could be enhanced when Pseudo SRAM is operated in normal mode (simulated with TSMC 100 nm technology model).