DocumentCode
2848461
Title
Synthesizing optimal family of linear systolic arrays for matrix computations
Author
Kumar, V. K Prasanna ; Tsai, Yu-Chen
Author_Institution
Univ. of Southern California, Los Angeles, CA, USA
fYear
1988
fDate
25-27 May 1988
Firstpage
51
Lastpage
60
Abstract
A method is proposed for designing a family of linear systolic arrays for matrix-oriented problems for which two-dimensional arrays have been designed. The design exhibits a tradeoff between local storage, s, and number of processing elements, n. The arrays are linear, with each processor having storage O(s),1>
Keywords
cellular arrays; parallel algorithms; linear systolic arrays; matrix computations; optimal family synthesis; processing elements; two-dimensional arrays; two-speed data streams; Algorithm design and analysis; Bandwidth; Delay; Design methodology; Fault tolerance; Parallel algorithms; Semiconductor device modeling; Systolic arrays; Two dimensional displays; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Systolic Arrays, 1988., Proceedings of the International Conference on
Conference_Location
San Diego, CA, USA
Print_ISBN
0-8186-8860-2
Type
conf
DOI
10.1109/ARRAYS.1988.18044
Filename
18044
Link To Document