• DocumentCode
    2848487
  • Title

    New architectures for systolic hashing

  • Author

    Panneerselvam, G. ; Jullien, G.A. ; Miller, W.C.

  • Author_Institution
    VLSI Res. Group, Windsor Univ., Ont., Canada
  • fYear
    1988
  • fDate
    25-27 May 1988
  • Firstpage
    73
  • Lastpage
    82
  • Abstract
    Two- and three-dimensional systolic architectures are proposed for the hash table data structure (hashing). The parallel systolic hashing architecture provides the facility for implementing the hash operations of Insert, Delete, and Member in a constant time complexity. The importance and advantages of extending sequential hashing to a parallelized form are discussed. An implementation is presented of a sorting problem of N numbers in an O(L) time complexity, where L is constant, using a three-dimensional parallelized systolic hashing process. This is compared to a sequential hashing process, which requires O(N) time complexity.<>
  • Keywords
    data structures; file organisation; sorting; Delete; Insert; Member; hash table data structure; sorting problem; systolic architectures; systolic hashing; Counting circuits; Data structures; Dictionaries; Fabrication; Information retrieval; Sorting; Systolic arrays; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Systolic Arrays, 1988., Proceedings of the International Conference on
  • Conference_Location
    San Diego, CA, USA
  • Print_ISBN
    0-8186-8860-2
  • Type

    conf

  • DOI
    10.1109/ARRAYS.1988.18046
  • Filename
    18046