DocumentCode
2848527
Title
Design and Implementation of Reconfigurable RSA Cryptosystem
Author
Chen, Yun-Lu ; Tseng, Chih-Yeh ; Chang, Hsie-Chia
Author_Institution
Nat. Chiao Tung Univ., Hsinchu
fYear
2007
fDate
25-27 April 2007
Firstpage
1
Lastpage
4
Abstract
In this paper, the hardware implementation of a reconfigurable RSA cryptosystem is presented. In order to match distinct security levels, the modified Montgomery modular multiplication algorithm is introduced into this 512/1024/2048/4096-bits RSA encryption/decryption. The huge number of register is also replaced by 5 memory blocks. As a result, our design including 5 memory blocks achieves the baud rate of 99 kb/s for 512-bit, 29 kb/s for 1024-bit, 6.8fcs/6 for 2048-bit and 1.7 kb/s for 4096-bit on Xilinx Vertex2 XC2V8000 of 6783 slices.
Keywords
cryptography; integrated logic circuits; Xilinx Vertex2 XC2V8000; modified Montgomery modular multiplication algorithm; reconfigurable RSA crypto system; word length 1024 bit; word length 2048 bit; word length 4096 bit; word length 512 bit; Design engineering; Distributed computing; Hardware; Information security; Internet; National security; Protection; Public key; Public key cryptography; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on
Conference_Location
Hsinchu
Print_ISBN
1-4244-0583-1
Electronic_ISBN
1-4244-0583-1
Type
conf
DOI
10.1109/VDAT.2007.373258
Filename
4239450
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