DocumentCode
2848540
Title
Performance evaluation of the HERMES multibit systolic array architecture for low level processing tasks
Author
Bourbakis, Nikolaos ; Barlos, Fotios
Author_Institution
Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
fYear
1988
fDate
25-27 May 1988
Firstpage
113
Lastpage
124
Abstract
The performance of the various parts of the HERMES multiprocessor vision system is evaluated. HERMES is an autonomous, hierarchical, heterogenic vision processing system, consisting of N/sup 2//4/sup i/, 0>
Keywords
computer vision; parallel architectures; performance evaluation; HERMES multibit systolic array architecture; low level processing tasks; multiprocessor vision system; performance evaluation; photoarrays; Computer architecture; Computer graphics; Computer vision; Image processing; Machine vision; Microprocessors; Pattern recognition; Systolic arrays; Tree graphs; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
Systolic Arrays, 1988., Proceedings of the International Conference on
Conference_Location
San Diego, CA, USA
Print_ISBN
0-8186-8860-2
Type
conf
DOI
10.1109/ARRAYS.1988.18052
Filename
18052
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