The novel Chinese abacus adder

Author

Zhao, Zi-Yi ; Lin, Chien-Hung ; Xie, Yu-Zhi ; Chen, Yen-Ju ; Lin, Yi-Jie ; Yi, Shu-Chung

Author_Institution

Nat. Changhua Univ. of Educ., Changhua

fYear

2007

fDate

25-27 April 2007

Firstpage

1

Lastpage

4

Abstract

A novel Chinese abacus adder is presented in this paper. The simulation results of 8-bit adders are compared with those of CLA (carry look-ahead) adder and RCA (ripple carry adder) by all input patterns. The delay of the 8-bit abacus adder is 22%, and 14% less than those of CLA adders for 0.35mum and 0.18mum technologies, respectively. The power consumption of the abacus adders are 30% and 60% less than those of CLA adders for 0.35mum, and 0.18mum technologies, respectively. The delay of the 32-bit abacus adder is 17%, and 12% less than those of CLA adder for 0.35mum, and 0.18mum technologies, respectively.

Keywords

CMOS logic circuits; adders; delays; digital arithmetic; 8-bit adders; CLA adders; CMOS technology; Carry Look-ahead adder; Chinese abacus adder; RCA adders; Ripple carry adder; delay; digital arithmetic circuits; power consumption; size 0.18 mum; size 0.35 mum; Adders; Circuits; Delay effects; Digital arithmetic; Energy consumption; Equations; Hydrogen; Propagation delay;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on

Conference_Location

Hsinchu

Print_ISBN

1-4244-0583-1

Electronic_ISBN

1-4244-0583-1

Type

conf

DOI

10.1109/VDAT.2007.372759

Filename

4239453