Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector

In this paper, a dual charge pump architecture for fast-lock low-jitter analog delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock analog DLL takes up less area compared to other similar fast lock analog DLL due to the reduction of the number of phase frequency detector (PFD) used in the design. An improved PFD is proposed to reduce the output jitter by reducing the one-shot pulse produced when the reference signal and output signal is in phase. The proposed DLL circuit is designed based on the Silterra 0.18-mum 1P6M CMOS process with a 1.8-V supply voltage. The active area of the proposed DLL circuit is 327.46 mum x 116.16 mum. An experimental chip was implemented and measured. The measurement results show that the proposed DLL has fast locking and low jitter properties.