Implementation of array structured maximum likelihood decoders

Author

Wen, Kuei-Ann ; Wang, Jhing-Fa ; Lee, Jau-Yien ; Lin, Ming-Yung

Author_Institution

Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

1988

fDate

25-27 May 1988

Firstpage

227

Lastpage

236

Abstract

Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay commutating switching processors for MLD have been concatenated to construct a pipeline MLD processor. The pipeline length can be adapted to meet the time/area constraints for various applications. A 2-D MLD array processor is also presented. Processing data are modulized, data transmission are embedded into processing elements, and a fixed-size 2-D MLD array is derived to meet high-data-throughput requirements.<>

Keywords

VLSI; decoding; parallel architectures; VLSI array processor architectures; array structured maximum likelihood decoders; data transmission; delay commutating switching processors; radix-4p processing elements; Communication switching; Concatenated codes; Data communication; Data processing; Delay; Maximum likelihood decoding; Pipelines; Throughput; Time factors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Systolic Arrays, 1988., Proceedings of the International Conference on

Conference_Location

San Diego, CA, USA

Print_ISBN

0-8186-8860-2

Type

conf

DOI

10.1109/ARRAYS.1988.18063

Filename

18063