Title :
A radiation hardened SRAM cell design in PD-SOI CMOS technology
Author :
Wang, Yiqi ; Li, Ying ; Zhao, Fazhan ; Liu, Mengxin ; Han, Zhengsheng
Author_Institution :
Inst. of Microelectron., Beijing, China
Abstract :
A miller MOS capacitor in PD-SOI process is introduced between the internal latch nodes of six transistor cells to improve SEU (Single Event Upset) immunity of SRAM cells. SPICE analysis of SEU sensitivity of proposed 6-T SRAM cell, which bases on device-physics-basic SPICE model in 0.35μm PD-SOI CMOS technology, indicates that the upset threshold of the proposed cell can reach to 36fC and increases by 33.3% than 6T without miller capacitor.
Keywords :
CMOS integrated circuits; MOS capacitors; SPICE; SRAM chips; flip-flops; radiation hardening (electronics); silicon-on-insulator; PD-SOI CMOS technology; PD-SOI process; SEU sensitivity; SPICE analysis; device-physics-basic SPICE model; internal latch node; miller MOS capacitor; radiation hardened SRAM cell design; single event upset immunity; size 0.35 mum; transistor cells; CMOS technology; Capacitance; Capacitors; MOS capacitors; Random access memory; SPICE; Single event upset; PD-SOI process; SEU; SPICE analysis; miller MOS capacitor; upset threshold;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of
Conference_Location :
Tianjin
Print_ISBN :
978-1-4577-1998-1
Electronic_ISBN :
Pending
DOI :
10.1109/EDSSC.2011.6117575
