Efficient systolic architecture for Hermitian eigenvalue problem

This paper presents an efficient systolic architecture for solving the Hermitian eigenvalue problem, which is a common issue in the spectrum sensing function of cognitive radio systems like WRANs. The designed architecture uses a novel upper triangular structure to improve performance with respect to the BLV array. The processing elements are based on sequential CORDIC processors to perform two complex Jacobi rotations. Tests and results show that the proposed architecture is suitable to design the spectrum sensing function of cognitive radio systems. The systolic architecture was described using generic structural VHDL and tested using an Altera FPGA.