Title :
An On-Chip Bus modeling and parameter simulation method based on utilization analysis
Author :
Shi, Zaifeng ; Li, Yuanqing ; Chen, Xing ; Yao, Suying
Author_Institution :
Sch. of Electron. Inf. & Eng., Tianjin Univ., Tianjin, China
Abstract :
It is necessary to estimate the system parameters such as bus utilization and buffer capacity In SoC architecture design. With the increase of complexity of system structure and communication protocol, the estimation becomes harder. The cycle-accurate modeling and simulation for the structure and data stream of On-Chip Bus is an efficient method to obtain the estimate value of above parameters. In this paper, this method is implemented by analyzing a Wishbone bus used in a Video Format Conversion chip, using Simulink. By comparing the simulation result and the pessimistic estimate value, the rationality and high efficiency of this method are verified. This method is suitable for analyzing various interconnecting architectures such as user-defined bus, industrial standard bus, multi-core and multi-bus system.
Keywords :
integrated circuit interconnections; parameter estimation; protocols; system-on-chip; SoC architecture design; buffer capacity; bus utilization analysis; communication protocol; cycle-accurate modeling; industrial standard bus interconnecting architecture; multibus interconnecting architecture; multicore interconnecting architecture; on-chip bus modeling; parameter simulation method; pessimistic estimate value; system parameter estimation; system structure complexity; user-defined bus interconnecting architecture; video format conversion chip; wishbone bus analysis; Bus Utilization; First-In-First-Out; On-Chip Bus; Parameter Simulation;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of
Conference_Location :
Tianjin
Print_ISBN :
978-1-4577-1998-1
Electronic_ISBN :
Pending
DOI :
10.1109/EDSSC.2011.6117580
