Parallel on Analog Circuit Synthesis

Analog circuit synthesis is a very important step of analog design automation flow. Due to the great effects on circuit performance degradation from the parasitic, it is a great time-consuming task, especially when the feature size is becoming smaller and smaller, operation frequency is becoming higher and higher, and the circuit scale is becoming larger and larger. In this paper, we present a parallel analog circuit synthesis flow with combination of functionality analysis based circuit partitioning, performance spec decomposition, test bench generation, and performance evaluation equation generation; it makes the high complex large scale circuit synthesis problem become multi low complex circuit synthesis problems of small scales, which enables parallel computing and speeds up the optimization process with full leverage of state-of-art computing resources through efficient task partitioning, management, and scheduling.