Title :
LVSMOS: an I/O-Cell-Friendly ESD and Latchup Robust Structure for CMOS Submicron Technologies with Compact Cell Design
Author_Institution :
Winbond Electron. Corp., Hsinchu
Abstract :
The ESD performance of standard CMOS I/O cells can be significantly enhanced by placing a shorted p-n diode adjacent to the NMOS connecting to the pad. The NMOS ESD is enhanced through vpnp holes injection into substrate and activation of an embedded SCR. Typically, It2 doubles with Vhold above VDD.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit design; semiconductor diodes; CMOS submicron technologies; I-O-cell-friendly ESD performance; LVSMOS; NMOS ESD; compact cell design; embedded SCR; latchup robust structure; shorted p-n diode; vpnp hole injection; Breakdown voltage; CMOS technology; Diodes; Electronics industry; Electrostatic discharge; Industrial electronics; Low voltage; MOS devices; Robustness; Thyristors;
Conference_Titel :
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0584-X
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2007.378919
