Title :
A 3D Packaging Technology for High-Density Stacked DRAM
Author_Institution :
NEC Electron., Sagamihara
Abstract :
A 3D packaging technology has been developed for high-density stacked DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using the so-called SMAFTI technology. A new bump and wiring structure for feedthrough interposer (FTI) has also been developed for fine-pitch and low-cost bonding.
Keywords :
DRAM chips; chip scale packaging; integrated circuit interconnections; microassembling; wafer level packaging; 3D packaging technology; SMAFTI technology; bump structure; chip interconnection; feedthrough interposer; high-density stacked DRAM chips; highly-doped poly-Si through-silicon vias technology; poly-Si filling; wafer level packaging; wiring structure; Assembly; Electronics packaging; Filling; Glass; National electric code; Random access memory; Resins; Through-silicon vias; Wafer bonding; Wiring;
Conference_Titel :
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0584-X
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2007.378921
