Challenges for Lithography Scaling to 32nm and Below

Microlithography continues to enable device scaling and manufacturing of high speed microprocessors, high density flash and DRAM memories, as well as SoCs and ASSPs. However, the shrink roadmaps of each device technology are diverging, with NAND flash leading, and application specific logic trailing. The implications of this divergence for developing lithography exposure tools to meet the needs of IC makers will be explored in this paper. Also, the status of immersion extension through the use of high index materials, the development of double patterning, and the growing acceptance of EUV technology will be reviewed.