Voltage scaling: key to embedded non-volatile memories in advanced CMOS

Author

Montree, André

Author_Institution

NXP Semicond., Eindhoven

fYear

2007

fDate

23-25 April 2007

Firstpage

1

Lastpage

2

Abstract

In this paper the voltage scaling of embedded non-volatile memories was discussed. Floating gate cells with high-K IPD and nitride trapping cells with high-K tunnel and blocking layers offer significant reduction of the program/erase efficiency. A major voltage reduction could be achieved by using phase change memory technology that is a serious contender for charge based embedded non-volatile memories in advanced sub-50 nm CMOS nodes. This paper also discusses experimental results, possibilities and challenges of memories to enable low voltage/power operation.

Keywords

CMOS memory circuits; dielectric materials; low-power electronics; power aware computing; random-access storage; CMOS; blocking layers; embedded nonvolatile memories; floating gate cells; high-K IPD; high-K tunnel layers; interpoly dielectric; low voltage/power operation; nitride trapping cells; phase change memory technology; program/erase efficiency; voltage scaling; CMOS technology; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Leakage current; Low voltage; Nonvolatile memory; Phase change memory; Temperature; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

1-4244-0584-X

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2007.378932

Filename

4239500