• DocumentCode
    2849335
  • Title

    A New Twin Flash Cell for 2 and 4 Bit Operation at 63nm Feature Size

  • Author

    Nagel, N. ; Müller, T. ; Isler, M. ; Pissors, V. ; Sachse, J.-U. ; Manger, D. ; Caspary, D. ; Parascandola, S. ; Olligs, D. ; Boubekeur, H. ; Heinrichsdorff, F. ; Bach, L. ; Polei, V. ; Gupta, J. ; Pritchard, D. ; Riedel, S. ; Strassburg, M. ; Deppe, J. ;

  • Author_Institution
    Qimonda, Dresden
  • fYear
    2007
  • fDate
    23-25 April 2007
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    A 63nm Twin Flash memory cell with a size of 0.0225 mum2 / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16 Gbit densities. To achieve small cell areas, a buried bit line and an aggressive gate length of ~100 nm are the key features of this 63nm Twin Flash cell. The cell is well capable of 2 and 4 bit operation.
  • Keywords
    flash memories; cell operation; high density nonvolatile memory products; key process features; size 63 nm; storage capacity 2 bit; storage capacity 4 bit; twin flash memory cell; Channel hot electron injection; Electric variables; Electron traps; Flash memory cells; Hot carriers; Isolation technology; Maintenance engineering; Silicon compounds; Tunneling; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    1524-766X
  • Print_ISBN
    1-4244-0584-X
  • Electronic_ISBN
    1524-766X
  • Type

    conf

  • DOI
    10.1109/VTSA.2007.378933
  • Filename
    4239501
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2849335