Author :
Nagel, N. ; Müller, T. ; Isler, M. ; Pissors, V. ; Sachse, J.-U. ; Manger, D. ; Caspary, D. ; Parascandola, S. ; Olligs, D. ; Boubekeur, H. ; Heinrichsdorff, F. ; Bach, L. ; Polei, V. ; Gupta, J. ; Pritchard, D. ; Riedel, S. ; Strassburg, M. ; Deppe, J. ;
Abstract :
A 63nm Twin Flash memory cell with a size of 0.0225 mum2 / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16 Gbit densities. To achieve small cell areas, a buried bit line and an aggressive gate length of ~100 nm are the key features of this 63nm Twin Flash cell. The cell is well capable of 2 and 4 bit operation.
Keywords :
flash memories; cell operation; high density nonvolatile memory products; key process features; size 63 nm; storage capacity 2 bit; storage capacity 4 bit; twin flash memory cell; Channel hot electron injection; Electric variables; Electron traps; Flash memory cells; Hot carriers; Isolation technology; Maintenance engineering; Silicon compounds; Tunneling; Voltage;
