• DocumentCode
    2849350
  • Title

    A Self-Aligned Contact Architecture with W-Gate for NOR Flash Technology Scaling

  • Author

    Blosse, A. ; Wei, M. ; Bhachawat, V. ; Hineman, M. ; Koval, R. ; Gorman, J. ; Kau, D. ; Tewg, J. ; Wang, L. ; Hajra, M. ; Schroeder, P. ; Woo, B.J. ; Fazio, A.

  • Author_Institution
    Intel Corp., Santa Clara
  • fYear
    2007
  • fDate
    23-25 April 2007
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    A self-aligned contact ETOXtrade flash memory process with W-gate capable of MLC operation is presented for the first time. Several key process elements were successfully integrated to achieve functional test structures. Significant cell area reduction can be realized using the SAC architecture by aggressive cell height scaling and thus this approach provides a manufacturable path for continued future scaling of flash memories.
  • Keywords
    CMOS memory circuits; flash memories; ETOX; NOR flash technology scaling; W-gate stack; flash memory process; functional test structures; self-aligned contact architecture; Etching; Flash memory; Oxidation; Plasma temperature; Rails; Semiconductor films; Silicon; Space technology; Temperature control; Thermal management;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    1524-766X
  • Print_ISBN
    1-4244-0584-X
  • Electronic_ISBN
    1524-766X
  • Type

    conf

  • DOI
    10.1109/VTSA.2007.378934
  • Filename
    4239502
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2849350