Author :
Blosse, A. ; Wei, M. ; Bhachawat, V. ; Hineman, M. ; Koval, R. ; Gorman, J. ; Kau, D. ; Tewg, J. ; Wang, L. ; Hajra, M. ; Schroeder, P. ; Woo, B.J. ; Fazio, A.
Abstract :
A self-aligned contact ETOXtrade flash memory process with W-gate capable of MLC operation is presented for the first time. Several key process elements were successfully integrated to achieve functional test structures. Significant cell area reduction can be realized using the SAC architecture by aggressive cell height scaling and thus this approach provides a manufacturable path for continued future scaling of flash memories.
Keywords :
CMOS memory circuits; flash memories; ETOX; NOR flash technology scaling; W-gate stack; flash memory process; functional test structures; self-aligned contact architecture; Etching; Flash memory; Oxidation; Plasma temperature; Rails; Semiconductor films; Silicon; Space technology; Temperature control; Thermal management;
